The invention is directed to a more efficient approach for performing pattern classification with respect to patterns in integrated circuit designs.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation.
An integrated circuit designer may use a set of EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. During this process, the design components are “placed” (i.e., given specific coordinate locations in the circuit layout) and “routed” (i.e., wired or connected together according to the designer's circuit definitions).
After an integrated circuit designer has created the circuit layout, verification and/or optimization operations are performed on the integrated circuit layout using a set of EDA testing and analysis tools. These actions are performed since significant variations from the as-designed IC product may occur to the as-manufactured IC product due to the optical and/or chemical nature of the processing used to manufacture the integrated circuit. For example, optical distortions during the lithography process may cause variations in feature dimensions (e.g. line widths) that are patterned using masks. Physical verification would occur to help identify areas of significant risks for problematic variations.
Many physical verification tools create markers at the location of potential violations. The problem is that there are often a very large number of these markers. It is difficult for either a human or an automated program to efficiently review these results and to perform analysis upon these markers. For example, one area of particular interest is the result of performing manufacturing hotspot analysis, where a verification tool is employed to check an electronic design for locations of potential manufacturability or printability problems (referred to as “hotspots”). Using such a tool, e.g., in combination with one or more respective models, the verification tool would identify and mark locations on the design in which there is a potential problem that would result when that design is manufactured. However, if the verification tool identifies millions of these locations and correspondingly inserts markers at all of those locations, and if it is necessary to inspect and analyze each and every one of those marked location, and if a certain amount of time is required to analyze those locations, then a large and excessive amount of time and system resources may be needed to analyze that design and those markers.
To address these problems, among others, the present invention in some embodiments provides an approach for performing pattern classification for electronic designs. One advantage of this invention is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.